The present invention relates generally to latching switches and more specifically to an improved fast turn-on latching switch.
Latching switches generally known as silicon controlled rectifier (SCR) is a four layer PNPN thyristor. The structure includes a P anode, an N anode gate, a P cathode gate and an N cathode. This SCR structure has advantages over most other solid state switches in its ability to pass a large current per unit area. For this reason SCR's are used in power driver circuits, which convert a logic level signal into a gate drive for power MOS's. For fast circuit operation, the turn-on time of the SCR should be minimized.
An SCR structure of the prior art which is compatible with the present integrated circuit processing techniques is illustrated in FIG. 1. An N- island 10 having a buried N+ layer 12 is dielectrically isolated from a support structure 14 by a dielectric isolation layer 16. An N+ cathode region 18 is formed in a P-cathode gate region 20 which also includes and P+ cathode gate contact region 22. The P+ anode 24 is formed in the N-anode gate region 10 as is an N+ anode gate contact region 28.
As illustrated in FIG. 2, the schematic of the SCR of FIG. 1 includes a vertical NPN transistor QV1 connected with a lateral PNP transistor QL2. The anode region 24 forms the emitter of transistor QL2, the anode gate or substrate 10 forms the base of QL2 and the cathode gate region 20 forms the collector of QL2. The cathode 18 forms the emitter of the vertical transistor QV1, cathode gate 20 forms the base of QV1 and the anode gate or substrate 10 forms the collector of QV1. The common uses of the anode gate or substrate 10 and cathode gate 20 forms the interconnection of the collector of QL2 to the base of QV1 and the collector of QV1 to the base of QL2. This interconnection forms a positive feedback loop. To turn the switch on, current is applied to either of the transistor bases. The SCR is not fully turned on until the signal propagates completely around the feedback loop illustrated in dash lines of FIG. 2.
For sake of clarity, the regions in the integrated circuit will be referred to using their transistor names instead of their SCR names and it is understood that they represent their respective SCR functions.
If for example, the turn-on signal is applied to the base of QV1 at region 22, there is a delay until the signal appears at the collector 10 of QV1. This time delay is the time it takes electrons being injected from the cathode or emitter 18 and diffusing through the base region 20 into the collector 10. This electron current then forward biases the emitter 24 base 10 junction of QL2 causing holes to be injected into the base region 10. These holes are then diffused through the base region 10 to be collected by the collector 20 of the lateral transistor QL2 which is also the base of QV1, which is a starting point. This ends the feedback loop. The turn-on time is proportional to the sum of both of the delays of the vertical Q1 and the lateral Q2.
It is known that for a fixed value Vbe, the base stored charge is proportional to base width and the collector current. Therefore, beta is inversely proportional to base width. This makes the base transient time inversely proportional to the base width squared. For a lateral transistor to vertical base width ratio in the order of 10, the difference between the lateral and vertical electrical parameters are significant. As illustrated in FIG. 1, the vertical base width WV1 is essentially small compared to the lateral base width WL2.
A solution to this problem is to form both the NPN and the PNP transistors as vertical device, thereby minimizing the base width and turn-on time. The merging of vertical PNP and NPN transistors has not been possible in planar processes to date.
Thus it is an object of the present invention to provide an integrated circuit having a vertical NPN and a vertical PNP integrated together to form a latching switch.
Another object of the present inventions is to improve the turn-on time of an SCR built in an integrated circuit.
Still another object of the present invention is to maximize the anode and cathode gate junction of an SCR per unit volume.
These and other objects are achieved by forming the latching switch having a vertical and lateral PNP connected in parallel with each other and having their bases connected to the collectors of parallel connected vertical and lateral NPN transistors and having their collectors connected to the bases of the NPN transistors. The PNP emitters form the anode, the PNP bases form the anode gate, the NPN bases form the cathode gate and the NPN emitters form the cathode of the latching switch. The vertical and lateral PNP's have a common base emitter junction and the vertical and lateral NPN's have a common base emitter junction The vertical and lateral PNP's have a common base region which has a junction with a collector region of the vertical PNP and a boundary with a collector region of the vertical NPN. The vertical and lateral NPN's have a common base region which has a junction with the collector region of the vertical NPN and a boundary with the collector region of the vertical PNP.
The integration in a planar process is achieved by having N and P wells contiguous at a first boundary and providing the appropriate base and emitter regions in the appropriate well to produce the vertical NPN and PNP transistors. The N anode gate region which forms the base of the vertical PNP is formed in the P well which forms the vertical collector and intersects the well boundary. The anode or P emitter region is formed in the base region. The P base region of the PNP vertical transistor is formed in the N well region and intersects the well boundary and has an N emitter region formed therein. The N base and P base region intersect the well boundary at distinct areas. Preferably the P emitter, N base, N emitter, and P base extend across the boundary into both P and N wells. This provides the four parallel, SCR connected transistors having equal base emitter junctions and having common base emitter junctions.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.